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| ht46r51a/ht46r52a a/d type 8-bit otp mcu rev. 1.30 1 march 6, 2009 general description the ht46r51a/ht46r52a are 8-bit high performance, risc architecture microcontroller devices specifically designed for a/d applications that interface directly to analog signals, such as those from sensors. the advan - tages of low power consumption, i/o flexibility, timer functions, oscillator options, multi-channel a/d con - verter, pulse width modulation function, halt and wake-up functions, watchdog timer, as well as low cost, enhance the versatility of these devices to suit a wide range of a/d application possibilities such as sensor signal processing, chargers, motor driving, industrial control, consumer products, subsystem controllers, etc. features low-power fully static cmos design operating voltage: f sys =4mhz: 2.2v~5.5v f sys =8mhz: 3.3v~5.5v program memory: 1k 15 otp (ht46r51a) 2k 15 otp (ht46r52a) data memory: 96 8 ram (ht46r51a) 128 8 ram (ht46r52a) a/d converter: 12bits 5ch external a/d converter reference voltage input pin 14 bidirectional i/o lines 1 interrupt input shared with an i/o line 8-bit programmable timer/event counter with over- flow interrupt and 8-stage prescaler on-chip crystal and rc oscillator 6-level subroutine nesting watchdog timer low voltage reset function halt function up to 0.5 s instruction cycle with 8mhz system clock at v dd =5v 1-channel 8-bit pwm output shared with an i/o line pfd function bit manipulation instruction table read instruction 63 powerful instructions all instructions in one or two machine cycles 16-pin nsop, 18-pin dip, 20-pin sop/ssop package technical document tools information faqs application note ha0003e communicating between the ht48 & ht46 series mcus and the ht93lc46 eeprom ha0004e ht48 & ht46 mcu uart software implementation method ha0084e nimh battery charger demo board - using the ht46r52 ha0075e mcu reset and oscillator circuits application note
block diagram pin assignment ht46r51a/ht46r52a rev. 1.30 2 march 6, 2009 ! " # $ % & $ ' ( ) * ) $ ' + , ) ) ( + * - . / * 0 + 1 , + / * 2 + 3 . 4 1 * & & & & - + - . & , + , + * 5 * - + ) * * ( 6 , + 2 + 3 4 & 0 + 0 0 + 1 - - + ) & + & + & - + - 7 4 3 2 , 0 - 0 , 2 3 4 7 8 - 8 7 4 3 2 , 0 0 , 2 3 4 7 8 - , + 2 + 3 4 & , + , 0 + 1 - - + ) & + & + & - + - 1 & 0 + 0 3 2 , 0 - 8 0 , 2 3 4 7 0 + 1 & + & - + - , + 2 + 3 - - + ) 4 pin description pin name i/o options description pa0~pa2 pa3/pfd pa4/tmr pa5/int pa6~pa7 i/o pull-high wake-up pa3 or pfd bidirectional 8-bit input/output port. each individual bit on this port can be config - ured as a wake-up input by configuration option. software instructions determine if the pin is a cmos output or schmitt trigger input. configuration options deter - mine which pins on this port have pull-high resistors. the pfd, tmr and external interrupt input are pin-shared with pa3, pa4, and pa5 respectively. pb0/an0 pb1/an1 pb2/an2 pb3/an3 pb4/an4 i/o pull-high bidirectional 5-bit input/output port. software instructions determine the cmos output or schmitt trigger input with or without pull-high resistor. configuration op - tions determine which pins on this port have pull-high resistors. pb is pin-shared with the a/d input pins. the a/d inputs are selected via software instructions once selected as an a/d input, the i/o function and pull-high resistor functions are disabled automatically. pd0/pwm i/o pull-high pd0 or pwm bidirectional 1-bit input/output port. software instructions determine the cmos output or schmitt trigger input with or without pull-high resistor. one configuration option determines which pin on this port has pull-high resistor. pd0 is pin-shared with the pwm output selected via configuration option. osc1 osc2 i o crystal or rc osc1, osc2 are connected to an external rc network or external crystal (deter - mined by configuration option) for the internal system clock. for external rc sys - tem clock operation, osc2 is an output pin for 1/4 system clock. res i schmitt trigger reset input, active low vdd positive power supply vss negative power supply, ground vref i a/d converter reference input voltage pins. connect this pin to the desired a/d reference voltage. the vref pin is connected to v dd for the 20-pin sop/ssop package absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +6.0v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature........................... 40 cto85 c i ol total ..............................................................150ma i oh total............................................................ 100ma total power dissipation .....................................500mw note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage f sys =4mhz 2.2 5.5 v f sys =8mhz 3.3 5.5 v i dd1 operating current (crystal osc) 3v no load, f sys =4mhz adc disabled 0.6 1.5 ma 5v 24ma i dd2 operating current (rc osc) 3v no load, f sys =4mhz adc disabled 0.8 1.5 ma 5v 2.5 4 ma i dd3 operating current 5v no load, f sys =8mhz adc disabled 48ma i stb1 standby current (wdt enabled) 3v no load, system halt 5 a 5v 10 a ht46r51a/ht46r52a rev. 1.30 3 march 6, 2009 symbol parameter test conditions min. typ. max. unit v dd conditions i stb2 standby current (wdt & ad disabled) 3v no load, system halt 1 a 5v 2 a v il1 input low voltage for i/o ports, tmr and int 0 0.3v dd v v ih1 input high voltage for i/o ports, tmr and int 0.7v dd v dd v v il2 input low voltage (res ) 0 0.4v dd v v ih2 input high voltage (res ) 0.9v dd v dd v v lvr low voltage reset voltage configuration option: 3v 2.7 3 3.3 v i ol i/o port sink current 3v v ol =0.1v dd 48 ma 5v 10 20 ma i oh i/o port source current 3v v oh =0.9v dd 2 4 ma 5v 5 10 ma r ph pull-high resistance of i/o ports 3v 20 60 100 k 5v 10 30 50 k v ad a/d input voltage 0 v ref v v ref adc input reference voltage range 1.2 vdd v dnl adc differential non-linear 2 lsb inl adc integral non-linear 2.5 4 lsb resolu resolution 12 bits i adc additional power consumption if a/d converter is used 3v 0.5 1 ma 5v 1.5 3 ma a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys1 system clock (crystal osc) 2.2v~5.5v 400 4000 khz 3.3v~5.5v 400 8000 khz f sys2 system clock (external rc osc) 5v ta=25c, external r erc =75k 20% typ. 4 +20% typ. mhz f timer timer i/p frequency (tmr) 2.2v~5.5v 0 4000 khz 3.3v~5.5v 0 8000 khz t wdtosc watchdog oscillator period 3v 45 90 180 s 5v 32 65 130 s t res external reset low pulse width 1 s t sst system start-up timer period wake-up from halt 1024 t sys t int interrupt pulse width 1 s t ad a/d clock period 1 s t adc a/d conversion time 80 t ad t adcs a/d sampling time 32 t ad t lvr low voltage width to reset 0.25 1 2 ms note: t sys =1/f sys ht46r51a/ht46r52a rev. 1.30 4 march 6, 2009 ht46r51a/ht46r52a rev. 1.30 5 march 6, 2009 functional description execution flow the system clock for the microcontroller is derived from either a crystal or an rc oscillator. the system clock is internally divided into four non-overlapping clocks. one instruction cycle consists of 4 system clock cycles. instruction fetching and execution are pipelined in such a way that a fetch and decoding takes an instruction cy - cle while execution take the next instruction cycle. the pipelining scheme causes each instruction to effectively execute in a cycle. if an instruction changes the program counter, two cycles are required to complete the instruc - tion. program counter pc for ht46r51a, the program counter (pc) is 10 bits wide and controls the sequence in which the instructions stored in the program rom are executed. the contents of the pc can specify a maximum of 1024 addresses. for ht46r52a, the program counter (pc) is 11 bits wide and controls the sequence in which the instructions stored in the program rom are executed. the contents of the pc can specify a maximum of 2048 addresses. after accessing a program memory word to fetch an in - struction code, the contents of the program counter are incremented by one. the program counter then points to the memory word containing the next instruction code. when executing a jump instruction, conditional skip ex - ecution, loading register, subroutine call or return from subroutine, initial reset, internal interrupt, external inter - rupt or return from interrupts, the pc manipulates the program transfer by loading the address corresponding to each instruction. the conditional skip is activated by instructions. once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. otherwise proceed to the next instruction. 0 , 0 , 0 , 1 # * * 9 : ; * * 9 < : 1 # * * 9 = : ; * * 9 : 1 # * * 9 = : ; * * 9 = : = = * ( > * 9 * ( : execution flow mode program counter *b10 *b9 *b8 *b7 *b6 *b5 *b4 *b3 *b2 *b1 *b0 initial reset 00000000000 external interrupt 00000000100 timer/event counter overflow 00000001000 a/d converter interrupt 00000001100 skip program counter+2 loading pcl pc10 pc9 pc8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: *b10~*b0: program counter bits s10~s0: stack register bits #10~#0: instruction code bits @7~@0: pcl bits, pc10~pc8: original pc counter, remain unchanged for the ht46r51a, since the program counter is 10 bits wide (b0~b9), the b10 columns in the table are not ap - plicable. for the ht46r52a, since the program counter is 11 bits wide (b0~b10) ht46r51a/ht46r52a rev. 1.30 6 march 6, 2009 the lower byte of the pc (pcl) is a readable and writeable register (06h). moving data into the pcl per - forms a short jump. the destination is within 256 loca - tions. when a control transfer takes place, an additional dummy cycle is required. program memory eprom the program memory is used to store the program in - structions which are to be executed. it also contains data, table, and interrupt entries, and is organized into 1024 15 (ht46r51a) or 2048 15 (ht46r52a) bits, addressed by the program counter and table pointer. certain locations in the rom are reserved for special usage: location 000h this location is reserved for program initialization. af - ter a chip reset, the program always begins execution at location 000h. location 004h this location is reserved for the external interrupt ser - vice program. if the int input pin is activated, the in - terrupt is enabled and the stack is not full, the program begins execution at this location. location 008h this location is reserved for the timer/event counter interrupt service program. if a timer interrupt results from a timer/event counter overflow, and the interrupt is enabled and the stack is not full, the program begins execution at location 008h. location 00ch location 00ch is reserved for the a/d converter inter - rupt service program. if an a/d converter interrupt re - sults from an end of a/d conversion, and if the interrupt is enabled and the stack is not full, the pro - gram begins execution at location 00ch. table location any location in the program memory can be used as look-up tables. the instructions tabrdc [m] (the current page) and tabrdl [m] (the last page) trans - fer the contents of the lower-order byte to the speci - fied data memory, and the higher-order byte to tblh (08h). the lower-order byte table pointer tblp (07h) are read/write registers, which indicate the table loca - tions. before accessing the table, the location has to be placed in tblp. the tblh is read only and cannot be restored. if the main routine and the isr (interrupt service routine) both employ the table read instruc - tion, the contents of the tblh in the main routine are likely to be changed by the table read instruction used in the isr. errors can occur. given this, using the ta - ble read instruction in the main routine and the isr si - multaneously should be avoided. however, if the table read instruction has to be applied in both main routine and the isr, the interrupt should be disabled prior to the table read instruction. it will not be enabled until the tblh in the main routine has been backed-up. all table related instructions require 2 cycles to complete the operation. 2 * ? 5 * ( @ * ; ( * * ? + 5 * * * ? * " > < * ? ( * 9 2 3 * a ! : " > < * ? ( * 9 2 3 * a ! : + * 5 * * ? - - b 0 - - b 1 1 b - - - b - - , b - - 7 b - - b - - b - , b - 7 b 0 1 1 b 2 * ? 5 * ( @ * ; ( * * ? + 5 * * * ? * " > < * ? ( * 9 2 3 * a ! : " > < * ? ( * 9 2 3 * a ! : + * 5 * * ? - - b 4 - - b 1 1 b - - - b - - , b - - 7 b - - b - - b - , b - 7 b 4 1 1 b program memory ht46r51a/ht46r52a rev. 1.30 7 march 6, 2009 instruction table location b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 tabrdc [m] p10 p9 p8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0 table location note: b10~b0: table location bits p10~p8: current program counter bits @7~@0: table pointer bits for the ht46r51a, since the program counter is 10 bits wide (b0~b9), the b10 column in the table are not appli - cable for the ht46r52a, since the program counter is 11 bits wide (b0~b10) stack register stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is organized into 6 levels and is neither part of the data nor part of the program space, and is neither read - able nor writeable. the activated level is indexed by the stack pointer (sp) and is neither readable nor writeable. at the state of a subroutine call or an interrupt acknowl - edgment, the contents of the program counter are pushed onto the stack. at the end of the subroutine or an interrupt routine, signaled by a return instruction (ret or reti), the program counter is restored to its previous value from the stack. after a chip reset, the sp will point to the top of the stack. if the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented (by ret or reti), the interrupt is serviced. this feature prevents stack overflow, allowing the programmer to use the structure more easily. if the stack is full and a call is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent 6 return addresses are stored). data memory ram the data memory (ram) is designed with 119 8 bits (ht46r51a), 151 8 bits (ht46r52a) and is divided into two functional groups, namely; special function reg - isters (23 8 bits) and general purpose data memory (96 8bit for ht46r51a, 128 8bit for ht46r52a) most of which are readable/writable, although some are read only. the unused space before 28h is reserved for fu - ture expanded usage and reading these locations will return the result 00h . the general purpose data mem - ory, addressed from 28h to 87h and 28h to a7h, is used for data and control information under instruction commands. all of the data memory areas can handle arithmetic, logic, increment, decrement and rotate oper - ations directly. except for some dedicated bits, each bit in the data memory can be set and reset by set [m].i and clr [m].i . they are also indirectly accessible through memory pointer registers (mp0;01h or mp1;03h). indirect addressing register location 00h and 02h are indirect addressing registers that are not physically implemented. any read/write op - eration of [00h] ([02h]) will access the data memory pointed to by mp0 (mp1). reading location 00h (02h) itself indirectly will return the result 00h . writing indi- rectly results in no operation. a configuration option se- lects whether the memory pointer registers, mp0 and mp1, are 7-bit or 8-bit. if selected to be 7-bit registers, then bit 7 of the memory pointers are not implemented. however, it must be noted that when the memory pointer for these devices is read, bit 7 will be read as a high value. note also that data memory addresses after address 80h cannot be accessed by mp0 and mp1, if mp0 and mp1 are selected as 7-bit registers. accumulator acc the accumulator closely relates to alu operations. it is also mapped to location 05h of the data memory which can operate with immediate data. the data move - ment between two data memories has to pass through the accumulator. arithmetic and logic unit alu this circuit performs 8-bit arithmetic and logic operations. the alu provides the following functions: arithmetic operations (add, adc, sub, sbc, daa) logic operations (and, or, xor, cpl) rotation (rl, rr, rlc, rrc) increment and decrement (inc, dec) branch decision (sz, snz, siz, sdz ....) the alu not only saves the results of a data operation but also changes the status register. ht46r51a/ht46r52a rev. 1.30 8 march 6, 2009 status register status this 8-bit register (0ah) contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf), and watchdog time-out flag (to). it also records the status information and controls the operation sequence. with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to and pdf flags. addition opera - tions related to the status register may give different re - sults from those intended. the to flag can be affected only by system power-up, a wdt time-out or executing the halt or clr wdt instruction. the pdf flag can be affected only by executing the halt or clr wdt instruction or a system power-up. the z, ov, ac, and c flags reflect the status of the latest operations. on entering the interrupt sequence or exe - cuting the subroutine call, the status register will not be automatically pushed onto the stack. if the contents of the status is important, and if the subroutine is likely to corrupt the status register, the programmer should take precautions and save it properly. ( * * - - b - b - b - 0 b - , b - 2 b - 3 b - 4 b - 7 b - 8 b - b - & b - b - b - b - 1 b - b b b 0 b , b 2 b 3 b 4 b 7 b 8 b b & b b b b 1 b c * ! ! * * d - - d - b b b 0 b , b 4 b 7 b 7 4 b ! * ! ! * * - - ! * ! ! * * " & " & " b & & ) " b % ( * * 9 8 3 * & : - - b - b - b - 0 b - , b - 2 b - 3 b - 4 b - 7 b - 8 b - b - & b - b - b - b - 1 b - b b b 0 b , b 2 b 3 b 4 b 7 b 8 b b & b b b b 1 b c * ! ! * * d - - d - b b b 0 b , b 4 b 7 b 4 b ! * ! ! * * - - ! * ! ! * * " & " & " b & & ) " b % ( * * 9 7 * & : ( * * ram mapping ht46r51a/ht46r52a rev. 1.30 9 march 6, 2009 interrupts the device provides an external interrupt, an internal timer/event counter interrupt, and an a/d converter in - terrupt. the interrupt control register (intc;0bh) con - tains the interrupt control bits to set the enable/disable and the interrupt request flags. once an interrupt subroutine is serviced, all the other in- terrupts will be blocked (by clearing the emi bit). this scheme may prevent any further interrupt nesting. other interrupt requests may occur during this interval but only the interrupt request flag is recorded. if a certain inter- rupt requires servicing within the service routine, the emi bit and the corresponding bit of the intc may be set to allow interrupt nesting. if the stack is full, the inter- rupt request will not be acknowledged, even if the re - lated interrupt is enabled, until the sp is decremented. if immediate service is desired, the stack must be pre - vented from becoming full. all these kinds of interrupts have a wake-up capability. as an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the pro - gram memory. only the program counter is pushed onto the stack. if the contents of the register or status register (status) are altered by the interrupt service program which corrupts the desired control sequence, the con - tents should be saved in advance. external interrupts are triggered by a high to low transi - tion of int and the related interrupt request flag (eif; bit 4 of the intc) will be set. when the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location 04h will occur. the interrupt request flag (eif) and emi bits will be cleared to disable other interrupts. the internal timer/event counter interrupt is initialized by setting the timer/event counter interrupt request flag (tf; bit 5 of the intc), which is normally caused by a timer overflow. after the interrupt is enabled, and the stack is not full, and the tf bit is set, a subroutine call to location 08h occurs. the related interrupt request flag (tf) is reset, and the emi bit is cleared to disable further maskable interrupts. the a/d converter interrupt is initialized by setting the a/d converter request flag (adf; bit 6 of the intc), caused by an end of a/d conversion. when the interrupt is enabled, the stack is not full and the adf is set, a sub- routine call to location 0ch will occur. the related in- terrupt request flag (adf) will be reset and the emi bit cleared to disable further interrupts. during the execution of an interrupt subroutine, other in - terrupt acknowledgments are held until the reti in - struction is executed or the emi bit and the related interrupt control bit are set to 1 (if the stack is not full). to return from the interrupt subroutine, ret or reti may be invoked. reti will set the emi bit to enable an in - terrupt service, but ret will not. interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding inter - rupts are enabled. in the case of simultaneous requests the following table shows the priority that is applied. these can be masked by resetting the emi bit. interrupt source priority vector external interrupt 1 04h timer/event counter overflow 2 08h a/d converter interrupt 3 0ch bit no. label function 0c c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. 1ac ac is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. 2 z z is set if the result of an arithmetic or logic operation is zero; otherwise z is cleared. 3ov ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. 4 pdf pdf is cleared by system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. 5to to is cleared by system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. 6~7 unused bit, read as 0 status (0ah) register ht46r51a/ht46r52a rev. 1.30 10 march 6, 2009 emi, eei, eti, and eadi are used to control the en - abling/disabling of interrupts. these bits prevent the re - quested interrupt from being serviced. once the interrupt request flags (tf, eif, and adf) are set, they will remain in the intc register until the interrupts are serviced or cleared by a software instruction. it is recommended that a program does not use the call subroutine within the interrupt subroutine. inter - rupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and enabling the interrupt is not well con- trolled, the original control sequence will be damaged once the call operates in the interrupt subroutine. oscillator configuration there are two oscillator circuits in the microcontroller. both of them are designed for system clocks, namely the external rc oscillator and the external crystal oscil - lator, which are determined by options. no matter what oscillator type is selected, the signal provides the sys - tem clock. the halt mode stops the system oscillator and ignores an external signal to conserve power. if an rc oscillator is used, an external resistor between osc1 and vss is required and the resistance must range from 24k to 1m . the system clock, divided by 4, is available on osc2 with pull-high resistor, which can be used to synchronize external logic. the rc os - cillator provides the most cost effective solution. however, the frequency of oscillation may vary with vdd, temperatures and the chip itself due to process variations. it is therefore not suitable for timing sensitive operations where an accurate oscillator frequency is de - sired. if the crystal oscillator is used, a crystal across osc1 and osc2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. instead of a crystal, a resona - tor can also be connected between osc1 and osc2 to get a frequency reference, but two external capacitors in osc1 and osc2 are required (if the oscillator can be disabled by options to conserve power). the wdt oscillator is a free running on-chip rc oscillator, and no external components are required. even if the sys- tem enters the power down mode, the system clock is stopped, but the wdt oscillator still works with a period of approximately 65 s at 5v. the wdt oscillator can be dis- abled by option to conserve power. watchdog timer wdt the clock source of the wdt is implemented by a dedi - cated rc oscillator (wdt oscillator) or instruction clock (system clock divided by 4) decided by options. this timer is designed to prevent a software mal-function or sequence jumping to an unknown location with unpre - dictable results. the watchdog timer can be disabled by an option. if the watchdog timer is disabled, all the exe - cutions related to the wdt result in no operation. the wdt clock (f s ) is further divided by an internal counter to give longer watchdog time-outs. the division ratio is fixed by an internal counter which gives a 2 15 fixed division ratio. once an internal wdt oscillator (rc oscillator with pe - riod of 65 s normally) is selected, it is divided by 2 16 to get the time-out period of approximately 4.3s. this time-out period may vary with temperature, vdd and process variations. bit no. label function 0 emi controls the master (global) interrupt (1= enable; 0= disable) 1 eei controls the external interrupt (1= enable; 0= disable) 2 eti controls the timer/event counter interrupt (1= enable; 0= disable) 3 eadi control the a/d converter interrupt (1= enable; 0= disable) 4 eif external interrupt request flag (1= active; 0= inactive) 5 tf internal timer/event counter request flag (1= active; 0= inactive) 6 adf a/d converter request flag (1= active; 0= inactive) 7 for test mode used only. must be written as 0 ; otherwise may result in unpredictable operation. intc (0bh) register ( * ( ( * ( ( $ ' + , , 4 - 1 system oscillator ht46r51a/ht46r52a rev. 1.30 11 march 6, 2009 if the wdt oscillator is disabled, the wdt clock may still come from the instruction clock and operate in the same manner except that in the halt state the wdt may stop counting and lose its protecting purpose. in this situation the logic can only be restarted by external logic. if the device operates in a noisy environment, using the on-chip rc oscillator (wdt osc) is strongly recom - mended, since the halt will stop the system clock. the wdt overflow under normal operation will initialize a chip reset and set the status bit to. whereas in the halt mode, the overflow will initialize a warm reset wherein only the program counter and sp are reset to zero. to clear the contents of the wdt, three methods are adopted; external reset (a low level to res ), soft - ware instructions, or a halt instruction. the software instructions include clr wdt and the other set clr wdt1 and clr wdt2. of these two types of instruc- tion, only one can be active depending on the option clr wdt times selection option .ifthe clr wdt is selected (i.e. clrwdt times equal one), any execution of the clr wdt instruction will clear the wdt. in case clr wdt1 and clr wdt2 are chosen (i.e. clrwdt times equal two), these two instructions must be executed to clear the wdt; otherwise, the wdt may reset the chip because of time-out. the wdt time-out period is fixed to f s /2 16 because the clr wdt or clr wdt1 and clr wdt2 instructions will clear the whole counter of the wdt. power down operation halt the halt mode is initialized by the halt instruction and results in the following... the system oscillator is turned off but the wdt oscil - lator keeps running (if the wdt oscillator or the real time clock is selected). the contents of the on-chip ram and registers remain unchanged the wdt and wdt prescaler will be cleared to zero. if the wdt clock source is from the rtc/wdt oscilla - tor, the wdt will remain active, and if the wdt clock source is f sys /4, the wdt will stop running. all of the i/o ports maintain their original status the pdf flag is set and the to flag is cleared the system quits the halt mode by way of an external reset, an interrupt, an external falling edge signal on port a or a wdt overflow. an external reset causes a device initialization and the wdt overflow performs a warm reset . after examining the to and pdf flags, the cause for a chip reset can be determined. the pdf flag is cleared by system power-up or by executing the clr wdt instruction and is set when executing the halt instruction. on the other hand, the to flag is set if the wdt time-out occurs, and causes a wake-up that only resets the program counter and sp, and leaves the oth - ers in their original status. the port a wake-up and interrupt methods can be con - sidered as a continuation of normal execution. each bit in port a can be independently selected to wake-up the device by options. awakening from an i/o port stimulus, the program resumes execution of the next instruction. on the other hand, awakening from an interrupt, two se- quence may occur. if the related interrupt is disabled or the interrupt is enabled but the stack is full, the program resumes execution at the next instruction. but if the in- terrupt is enabled, and the stack is not full, the regular in- terrupt response takes place. when an interrupt request flag is set before entering the halt status, the system cannot be awakened using that interrupt. if wake-up events occur, it takes 1024 t sys (system clock period) to resume normal operation. in other words, a dummy pe - riod is inserted after the wake-up. if the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution is delayed by more than one cycle. however, if the wake-up results in the next instruction execution, the execution will be performed immediately after the dummy period is finished. to minimize power consumption, all the i/o pins should be carefully managed before entering the halt status. reset there are three ways in which a reset may occur: res reset during normal operation res reset during halt wdt time-out reset during normal operation the wdt time-out during halt differs from other chip reset conditions, for it can perform a warm reset that resets only the program counter and sp, leaving the other circuits at their original state. some registers re - main unaffected during any other reset conditions. most registers are reset to the initial condition when the re - ) * $ ( " " * ) * 1 ( " * ) * 1 ( * * * $ ' + , ) * ( ( 7 < ? * $ " * ) * < 4 < ? * $ + 7 9 $ + 3 : watchdog timer ht46r51a/ht46r52a rev. 1.30 12 march 6, 2009 set conditions are met. examining the pdf and to flags, the program can distinguish between different chip resets. to pdf reset conditions 0 0 res reset during power-up u u res reset during normal operation 0 1 res wake-up halt 1 u wdt time-out during normal operation 1 1 wdt wake-up halt note: u stands for unchanged to guarantee that the system oscillator is started and stabilized, the sst (system start-up timer) provides an extra-delay of 1024 system clock pulses when the sys - tem reset (power-up, wdt time-out or res reset) or the system awakes from the halt state. when a system re - set occurs, the sst delay is added during the reset pe - riod. any wake-up from the halt will enable the sst delay. an extra option load time delay is added during system reset (power-up, wdt time-out at normal mode or res reset). the functional unit chip reset status are shown below. program counter 000h interrupt disable prescaler, divider cleared wdt clear. after master reset, wdt begins counting timer/event counter off input/output ports input mode stack pointer points to the top of the stack - - > - > - e - 1 - - > - e 1 - e 1 ! reset circuit note: most applications can use the basic reset cir - cuit as shown, however for applications with ex - tensive noise, it is recommended to use the hi-noise reset circuit. ) * ) b " ( ! a < * - < ? * ( ) ; ( < reset configuration = * < # * * reset timing chart the register states are summarized below: register reset(power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* tmr xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmrc 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu program counter 0000h 0000h 0000h 0000h 0000h mp0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu mp1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu intc -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu ht46r51a/ht46r52a rev. 1.30 13 march 6, 2009 register reset(power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---u uuuu pbc ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---u uuuu pd ---- ---1 ---- ---1 ---- ---1 ---- ---1 ---- ---u pdc ---- ---1 ---- ---1 ---- ---1 ---- ---1 ---- ---u pwm xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrl xxxx ---- xxxx ---- xxxx ---- xxxx ---- uuuu ---- adrh xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adcr 0100 0000 0100 0000 0100 0000 0100 0000 uuuu uuuu acsr ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu note: * stands for warm reset u stands for unchanged x stands for unknown timer/event counter only one timer/event counter (tmr) are implemented in the microcontroller. the timer/event counter contains an 8-bit programmable count-up counter and the clock may come from an external source or an internal clock source. an internal clock source comes from f sys . the external clock input allows the user to count external events, measure time intervals or pulse widths, or to generate an accurate time base. there are two registers related to the timer/event coun- ter; tmr (0dh), tmrc (0eh). writing tmr will transfer the specified data to timer/event counter registers. reading the tmr will read the contents of the timer/event counter. the tmrc is a control register, which defines the operating mode, counting enable or disable and an active edge. the tm0 and tm1 bits define the operation mode. the event count mode is used to count external events, which means that the clock source is from an external (tmr) pin. the timer mode functions as a normal timer with the clock source coming from the internal selected clock source. finally, the pulse width measurement mode can be used to count the high or low level duration of the external signal (tmr), and the counting is based on the internal selected clock source. in the event count or timer mode, the timer/event coun - ter starts counting at the current contents in the timer/event counter and ends at ffh . once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt re - quest flag (tf; bit 5 of the intc ). in the pulse width measurement mode with the values of the ton and te bits equal to 1, after the tmr has received a transient from low to high (or high to low if the te bit is 0 ), it will start counting until the tmr returns to the original level and resets the ton. the measured result remains in the timer/event counter even if the activated transient oc- curs again. in other words, only 1-cycle measurement can be made until the ton is set. the cycle measure- ment will re-operate as long as it receives further tran- sient pulse. in this operation mode, the timer/event counter begins counting not according to the logic level but to the transient edges. in the case of counter over- flows, the counter is reloaded from the timer/event coun - ter register and issues an interrupt request, as in the other two modes, i.e., event and timer modes. to enable the counting operation, the timer on bit (ton; bit 4 of the tmrc) should be set to 1 .inthe pulse width measurement mode, the ton is automati - cally cleared after the measurement cycle is completed. but in the other two modes, the ton can only be reset by instructions. the overflow of the timer/event counter is one of the wake-up sources and can also be applied to a pfd (programmable frequency divider) output at pa3 by options. no matter what the operation mode is, writing a 0 to eti (bit2 of the intc) disables the re - lated interrupt service. when the pfd function is se - lected, executing set [pa].3 instruction to enable the pfd output and executing clr [pa].3 instruction to disable the pfd output. in the case of timer/event counter off condition, writing data to the timer/event counter preload register also re - loads that data to the timer/event counter. but if the timer/event counter is turn on, data written to the ht46r51a/ht46r52a rev. 1.30 14 march 6, 2009 timer/event counter is kept only in the timer/event coun - ter preload register. the timer/event counter still contin - ues its operation until an overflow occurs. when the timer/event counter (tmr) is read, the clock is blocked to avoid errors, as this may results in a counting error. blocking of the clock issue should be taken into account by the programmer. it is strongly recommended to load a desired value into the tmr register first, before turning on the related timer/event counter, for proper op - eration since the initial value of tmr is unknown. due to the timer/event scheme, the programmer should pay special attention on the instruction to enable then dis - able the timer for the first time, whenever there is a need to use the timer/event function, to avoid unpredictable result. after this procedure, the timer/event function can be operated normally. the bit0~bit2 of the tmrc can be used to define the pre-scaling stages of the internal clock sources of the timer/event counter. the definitions are as shown. the overflow signal of the timer/event counter can be used to generate the pfd signal. the timer prescaler is also used as the pwm counter. * + 5 * ! * ( ( ! * + 5 * & ( ! 5 $ ( a * * * * 7 < * ( . - 7 < & * + 5 * - * * $ ' 1 8-bit timer/event counter structure bit no. label function 0 1 2 psc0 psc1 psc2 defines the prescaler stages, psc2, psc1, psc0= 000: f int =f sys 001: f int =f sys /2 010: f int =f sys /4 011: f int =f sys /8 100: f int =f sys /16 101: f int =f sys /32 110: f int =f sys /64 111: f int =f sys /128 3te defines the tmr active edge of the timer/event counter: in event counter mode (tm1,tm0)=(0,1): 1:count on falling edge; 0:count on rising edge in pulse width measurement mode (tm1,tm0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge 4 ton enable/disable timer counting (0=disable; 1=enable) 5 unused bit, read as 0 6 7 tm0 tm1 defines the operating mode, tm1, tm0: 01=event count mode (external clock) 10=timer mode (internal clock) 11=pulse width measurement mode 00=unused tmrc (0eh) register ht46r51a/ht46r52a rev. 1.30 15 march 6, 2009 input/output ports there are 14 bidirectional input/output lines in the , labeled as pa, pb and pd, which are mapped to the data memory of [12h], [14h] and [18h] respectively. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, that is, the inputs must be ready at the t2 rising edge of instruction mov a,[m] (m=12h, 14h or 18h). for output operation, all the data is latched and remains unchanged until the output latch is rewritten. each i/o line has its own control register (pac, pbc, pdc) to control the input/output configuration. with this control register, cmos output or schmitt trigger input with or without pull-high resistor structures can be re - configured dynamically under software control. to func - tion as an input, the corresponding latch of the control register must write 1 . the input source also depends on the control register. if the control register bit is 1, the input will read the pad state. if the control register bit is 0 , the contents of the latches will move to the inter - nal bus. the latter is possible in the read-modify-write instruction. for output function, cmos is the only configuration. these control registers are mapped to locations 13h, 15h and 19h. after a chip reset, these input/output lines remain at high levels or floating state (dependent on pull-high options). each bit of these input/output latches can be set or cleared by set [m].i and clr [m].i (m=12h, 14h or 18h) instructions. some instructions first input data and then follow the output operations. for example, set [m].i , clr [m].i, cpl [m], cpla [m] read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. each line of port a has the capability of waking-up the device. each i/o port has a pull-high option. once the pull-high option is selected, the i/o port has a pull-high resistor, otherwise, there s none. take note that a non- pull-high i/o port operating in input mode will cause a floating state. the pa3, pa4 and pa5 are pin-shared with pfd, tmr and int pins respectively. if the pfd option is selected, the output signal in output mode of pa3 will be the pfd signal generated by the timer/event counter overflow signal. the input mode al - ways remain in its original functions. once the pfd op - tion is selected, the pfd output signal is controlled by the pa3 data register only. the i/o functions of pa3 are shown below. i/o mode i/p (normal) o/p (normal) i/p (pfd) o/p (pfd) pa3 logical input logical output logical input pfd (timer on) note: the pfd frequency is the timer/event counter overflow frequency divided by 2. * 9 1 * * ) : ) > < * $ * 2 * ) > < * 9 * ( : ! * * ( * & ( ( < # # * & ) * ( * # * ! * ( * ) * * * & - . 0 + 1 , + 2 + 3 4 & - + - . & , + , - + ) * * * * * * * * * * * * * * * * * f 0 / * 1 g * * * * f - / ) g h 6 h h 6 h * $ * , input/output ports ht46r51a/ht46r52a rev. 1.30 16 march 6, 2009 the definitions of the pfd control signal and pfd output frequency are listed in the following table. timer timer preload value pa3 data register pa3 pad state frequency off x 0 0 x off x 1 u x on n 0 0 x on n 1 pfd f int /(2(256-n)) note: x stands for unused u stands for unknown n is the preload value for the timer/event counter f tmr is the input clock frequency for the timer/event counter the pb can also be used as a/d converter inputs. the a/d function will be described later. there is a pwm function shared with pd0. if the pwm function is en - abled, the pwm signal will appear on pd0 (if pd0 is op - erating in output mode). the i/o functions of pd0 are as shown. i/o mode i/p (normal) o/p (normal) i/p (pwm) o/p (pwm) pd0 logical input logical output logical input pwm it is recommended that unused or not bonded out i/o lines should be set as output pins by software instruction to avoid consuming power under input floating state. pwm the microcontroller provides one channel pwm output shared with pd0. the pwm supports 6+2 mode. the pwm channel has their data register denoted as pwm(1ah). the frequency source of the pwm counter comes from f sys . the pwm register is an 8-bit register. the waveforms of the pwm outputs are as shown. once the pd0 are selected as the pwm outputs and the output function of the pd0 are enabled (pdc.0= 0), writing 1 to pd0 data register will enable the pwm out - put function and writing 0 will force the pd0 to stay at 0. a (6+2) bits mode pwm cycle is divided into four modu - lation cycles (modulation cycle 0~modulation cycle 3). each modulation cycle has 64 pwm input clock period. in a (6+2) bit pwm function, the contents of the pwm register is divided into two groups. group 1 of the pwm register is denoted by dc which is the value of pwm.7~pwm.2. the group 2 is denoted by ac which is the value of pwm.1~pwm.0. in a (6+2) bits mode pwm cycle, the duty cycle of each modulation cycle is shown in the table. parameter ac (0~3) duty cycle modulation cycle i (i=0~3) i ht46r51a/ht46r52a rev. 1.30 18 march 6, 2009 pcr2 pcr1 pcr0 43210 0 0 0 pb4 pb3 pb2 pb1 pb0 0 0 1 pb4 pb3 pb2 pb1 an0 0 1 0 pb4 pb3 pb2 an1 an0 0 1 1 pb4 pb3 an2 an1 an0 1 0 0 pb4 an3 an2 an1 an0 1 0 1 an4 an3 an2 an1 an0 110 undefined, cannot be used 111 port b configuration + * 5 * + * 5 * + * 5 * - - - & - - - & - - & - - & & . - . - a < ! * $ * + 5 c * $ * & * $ c * ( * ( * # ( + * ( > * * ? * $ ' + / * $ ' + 7 * * $ ' + 0 i 0 i 7 - c * * $ * + 5 * + 5 + * ( * * * * - - & - - - & * $ * + 5 * + 5 - - - & e * & * * * * + e * + * 5 * * a ! * $ $ * * * * * ! * a * - & - - & * $ * + 5 * + 5 ! j * ! * $ * + 5 ! * $ * + 5 * * * ( * ! ! / * ; * * * ( * ( ( a ! + * ( * * * * + * ( * * * * a/d conversion timing the following two programming examples illustrate how to setup and implement an a/d conversion. in the first exam - ple, the method of polling the eocb bit in the adcr register is used to detect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using eocb polling method to detect end of conversion clr eadi ; disable adc interrupt mov a,00000001b mov acsr,a ; setup the acsr register to select f sys /8 as the a/d clock mov a,00100000b ; setup adcr register to configure port pb0~pb3 as a/d inputs mov adcr,a ; and select an0 to be connected to the a/d converter : : ; as the port b channel bits have changed the following start ; signal (0-1-0) must be issued within 10 instruction cycles : start_conversion: clr start set start ; reset a/d clr start ; start a/d polling_eoc: sz eocb ; poll the adcr register eocb bit to detect end of a/d conversion jmp polling_eoc ; continue polling mov a,adrh ; read conversion result high byte value from the adrh register mov adrh_buffer,a ; save result to user defined memory mov a,adrl ; read conversion result low byte value from the adrl register mov adrl_buffer,a ; save result to user defined memory ht46r51a/ht46r52a rev. 1.30 19 march 6, 2009 : : jmp start_conversion ; start next a/d conversion example: using interrupt method to detect end of conversion clr eadi ; disable adc interrupt mov a,00000001b mov acsr,a ; setup the acsr register to select f sys /8 as the a/d clock mov a,00100000b ; setup adcr register to configure port pb0~pb3 as a/d inputs mov adcr,a ; and select an0 to be connected to the a/d converter : ; as the port b channel bits have changed the following start ; signal (0-1-0) must be issued within 10 instruction cycles : start_conversion: clr start set start ; reset a/d clr start ; start a/d clr adf ; clear adc interrupt request flag set eadi ; enable adc interrupt set emi ; enable global interrupt : : : ; adc interrupt service routine adc_isr: mov acc_stack,a ; save acc to user defined memory mov a,status mov status_stack,a ; save status to user defined memory : : mov a,adrh ; read conversion result high byte value from the adrh register mov adrh_buffer,a ; save result to user defined register mov a,adrl ; read conversion result low byte value from the adrl register mov adrl_buffer,a ; save result to user defined register clr start set start ; reset a/d clr start ; start a/d : : exit_int_isr: mov a,status_stack mov status,a ; restore status from user defined memory mov a,acc_stack ; restore acc from user defined memory reti low voltage reset lvr there is a low voltage reset circuit (lvr) implemented in the microcontrollers. the function can be enabled/dis - abled by options. if the supply voltage of the device is within the range 0.9v~v lvr such as changing a battery, the lvr will au - tomatically reset the device internally. the lvr includes the following specifications: the low voltage (0.9v~v lvr ) has to remain in their original state to exceed 1ms. if the low voltage state does not exceed 1ms, the lvr will ignore it and do not perform a reset function. the lvr uses the or function with the external res signal to perform chip reset. the relationship between v dd and v lvr is shown below. note: v opr is the voltage range for proper chip operation at 4mhz system clock. 2 e 2 0 e - e - e 8 " 2 e 2 ht46r51a/ht46r52a rev. 1.30 20 march 6, 2009 2 e 2 " - e 8 - * ( k k ( * " * * ( low voltage reset note: *1: to make sure that the system oscillator has stabilized, the sst provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: since low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay, the device enters the reset mode. options the following shows kinds of options in the device. all the options must be defined to ensure having a proper function - ing system. options osc type selection. this option is to decide if an rc or crystal oscillator is chosen as system clock. wdt source selection. there are three types of selection: on-chip rc oscillator, instruction clock or disable the wdt. clrwdt times selection. this option defines how to clear the wdt by instruction. one time means that the clr wdt instruction can clear the wdt. two times means only if both of the clr wdt1 and clr wdt2 instructions have been executed, then wdt can be cleared. wake-up selection. this option defines the wake-up function activity. external i/o pins (pa only) all have the capability to wake-up the chip from a halt by a falling edge. (bit option) pull-high selection. this option is to decide whether a pull-high resistance is visible or not in the input mode of the i/o ports. pa, pb and pd are bit option. pfd selection. pa3: level output or pfd output. pwm selection. pd0: level output or pwm output lvr selection. enable or disable lvr function. mp0/mp1 7-bit or 8-bit selection. if mp0 and mp1 are selected as 7-bit registers, then data memory addresses after 80h cannot be accessed by mp0 and mp1. application circuits note: 1. crystal/resonator system oscillators for crystal oscillators, c1 and c2 are only required for some crystal frequencies to ensure oscillation. for resonator applications c1 and c2 are normally required for oscillation to occur. for most applications it is not necessary to add r1. however if the lvr function is disabled, and if it is required to stop the oscillator when vdd falls below its operating range, it is recommended that r1 is added. the values of c1 and c2 should be selected in consultation with the crystal/resonator manufacturer specifications. 2. reset circuit the reset circuit resistance and capacitance values should be chosen to ensure that vdd is stable and re- mains within its operating voltage range before the res pin reaches a high level. ensure that the length of the wiring connected to the res pin is kept as short as possible, to avoid noise interference. 3. for applications where noise may interfere with the reset circuit and for details on the oscillator external com- ponents, refer to application note ha0075e for more information. ht46r51a/ht46r52a rev. 1.30 21 march 6, 2009 ! " # # $ % & ' ( ) ' ! * " $ $ * $ + , ht46r51a/ht46r52a rev. 1.30 22 march 6, 2009 instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of pro - gram instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of pro - gramming overheads. for easier understanding of the various instruction codes, they have been subdivided into several func - tional groupings. instruction timing most instructions are implemented within one instruc - tion cycle. the exceptions to this are branch, call, or ta - ble read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5 s and branch or call instructions would be im - plemented within 1 s. although instructions which re - quire one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instruc- tions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to imple- ment. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instruc- tions would be clr pcl or mov pcl, a . for the case of skip instructions, it must be noted that if the re- sult of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific imme - diate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to en - sure correct handling of carry and borrow data when re - sults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on pro - gram requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a sub- routine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the sub - routine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made re - garding the condition of a certain data memory or indi - vidual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the pro - gram perhaps determined by the condition of certain in - put switches or by the condition of internal data bits. ht46r51a/ht46r52a rev. 1.30 23 march 6, 2009 bit operations the ability to provide single bit operations on data mem - ory is an extremely flexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the fea - ture removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write pro - cess is taken care of automatically when these bit oper - ation instructions are used. table read operations data storage is normally implemented by using regis - ters. however, when working with large amounts of fixed data, the volume involved often makes it inconve - nient to store the fixed data in the data memory. to over - come this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instruc - tions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt in - struction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electro - magnetic environments. for their relevant operations, refer to the functional related sections. instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be con - sulted as a basic instruction reference using the follow - ing listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z ht46r51a/ht46r52a rev. 1.30 24 march 6, 2009 mnemonic description cycles flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read table (current page) to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf flags remain unchanged. instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc acc+[m]+c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m] acc+[m]+c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc acc+x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m] acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) z ht46r51a/ht46r52a rev. 1.30 25 march 6, 2009 call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then in - crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruc - tion. operation stack program counter + 1 program counter addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m] 00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc- tion with clr wdt2 and must be executed alternately with clr wdt2 to have effect. re- petitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc - tion with clr wdt1 and must be executed alternately with clr wdt1 to have effect. re - petitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf ht46r51a/ht46r52a rev. 1.30 26 march 6, 2009 cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value re - sulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by add - ing 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to 0 pdf 1 affected flag(s) to, pdf ht46r51a/ht46r52a rev. 1.30 27 march 6, 2009 inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m] [m]+1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accumu - lator. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m] acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or oper - ation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) z ht46r51a/ht46r52a rev. 1.30 28 march 6, 2009 or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or op - eration. the result is stored in the accumulator. operation acc acc or x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or oper - ation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter stack acc x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed be- fore returning to the main program. operation program counter stack emi 1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory re - main unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 affected flag(s) none ht46r51a/ht46r52a rev. 1.30 29 march 6, 2009 rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 affected flag(s) c ht46r51a/ht46r52a rev. 1.30 30 march 6, 2009 sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the data memory. note that if the re - sult of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] 1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] 1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) none ht46r51a/ht46r52a rev. 1.30 31 march 6, 2009 siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m]+1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in - struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m]+1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is nega - tive, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc x affected flag(s) ov, z, ac, c ht46r51a/ht46r52a rev. 1.30 32 march 6, 2009 swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruc - tion. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none ht46r51a/ht46r52a rev. 1.30 33 march 6, 2009 xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor op - eration. the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor op - eration. the result is stored in the data memory. operation [m] acc xor [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected flag(s) z ht46r51a/ht46r52a rev. 1.30 34 march 6, 2009 package information 16-pin nsop (150mil) outline dimensions ms-012 symbol dimensions in mil min. nom. max. a 228 244 b 150 157 c12 20 c 386 394 d 69 e 50 f4 10 g16 50 h7 10 08 ht46r51a/ht46r52a rev. 1.30 35 march 6, 2009 3 8 7 & 1 % b j 18-pin dip (300mil) outline dimensions ms-001d (see fig1) symbol dimensions in mil min. nom. max. a 880 920 b 240 280 c 115 195 d 115 150 e14 22 f45 70 g 100 h 300 325 i 430 ms-001d (see fig2) symbol dimensions in mil min. nom. max. a 845 880 b 240 280 c 115 195 d 115 150 e14 22 f45 70 g 100 h 300 325 i 430 ht46r51a/ht46r52a rev. 1.30 36 march 6, 2009 7 - 8 & 1 % b fig1. full lead packages 7 - 8 & 1 % b fig2. 1 / 2 lead packages mo-095a (see fig2) symbol dimensions in mil min. nom. max. a 845 885 b 275 295 c 120 150 d 110 150 e14 22 f45 60 g 100 h 300 325 i 430 ht46r51a/ht46r52a rev. 1.30 37 march 6, 2009 20-pin sop (300mil) outline dimensions ms-013 symbol dimensions in mil min. nom. max. a 393 419 b 256 300 c12 20 c 496 512 d 104 e 50 f4 12 g16 50 h8 13 08 ht46r51a/ht46r52a rev. 1.30 38 march 6, 2009 - - & 1 j % b 20-pin ssop (150mil) outline dimensions symbol dimensions in mil min. nom. max. a 228 244 b 150 158 c8 12 c 335 347 d49 65 e 25 f4 10 g15 50 h7 10 08 ht46r51a/ht46r52a rev. 1.30 39 march 6, 2009 - - & 1 j % b product tape and reel specifications reel dimensions sop 16n (150mil), ssop 20s (150mil) symbol description dimensions in mm a reel outer diameter 330.0 1.0 b reel inner diameter 100.0 1.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.0 0.5 t1 space between flange 16.8 +0.3/-0.2 t2 reel thickness 22.2 0.2 sop 20w symbol description dimensions in mm a reel outer diameter 330.0 1.0 b reel inner diameter 100.0 1.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.0 0.5 t1 space between flange 24.8 +0.3/-0.2 t2 reel thickness 30.2 0.2 ht46r51a/ht46r52a rev. 1.30 40 march 6, 2009 & carrier tape dimensions sop 16n (150mil) symbol description dimensions in mm w carrier tape width 16.0 0.3 p cavity pitch 8.0 0.1 e perforation position 1.75 0.1 f cavity to perforation (width direction) 7.5 0.1 d perforation diameter 1.55 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.0 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 6.5 0.1 b0 cavity width 10.3 0.1 k0 cavity depth 2.1 0.1 t carrier tape thickness 0.30 0.05 c cover tape width 13.3 0.1 ht46r51a/ht46r52a rev. 1.30 41 march 6, 2009 ) - 1 6 - & - - * > * * * ! * # * ( * # ( * ( ! * * # * * ! e ( * b ( sop 20w symbol description dimensions in mm w carrier tape width 24.0 +0.3/-0.1 p cavity pitch 12.0 0.1 e perforation position 1.75 0.10 f cavity to perforation (width direction) 11.5 0.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 10.8 0.1 b0 cavity width 13.3 0.1 k0 cavity depth 3.2 0.1 t carrier tape thickness 0.30 0.05 c cover tape width 21.3 0.1 ssop 20s (150mil) symbol description dimensions in mm w carrier tape width 16.0 +0.3/-0.1 p cavity pitch 8.0 0.1 e perforation position 1.75 0.10 f cavity to perforation (width direction) 7.5 0.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 6.5 0.1 b0 cavity width 9.0 0.1 k0 cavity depth 2.3 0.1 t carrier tape thickness 0.30 0.05 c cover tape width 13.3 0.1 ht46r51a/ht46r52a rev. 1.30 42 march 6, 2009 ht46r51a/ht46r52a rev. 1.30 43 march 6, 2009 copyright 2009 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shanghai sales office) g room, 3 floor, no.1 building, no.2016 yi-shan road, minhang district, shanghai, china 201103 tel: 86-21-5422-4590 fax: 86-21-5422-4705 http://www.holtek.com.cn holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, gaoxin m 2nd, middle zone of high-tech industrial park, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor inc. (beijing sales office) suite 1721, jinyu tower, a129 west xuan wu men street, xicheng district, beijing, china 100031 tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 fax: 86-10-6641-0125 holtek semiconductor inc. (chengdu sales office) 709, building 3, champagne plaza, no.97 dongda street, chengdu, sichuan, china 610016 tel: 86-28-6653-6590 fax: 86-28-6653-6591 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538, usa tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com |
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